In high density memory systems, a typical non-volatile memory cell may include a metal-oxide semiconductor field effect transistor (MOSFET) having a parameter, e.g., a transistor device threshold voltage (Vt), that may be varied for storing desired information, e.g., by injecting charges into a floating gate or gate oxide. Accordingly, a current sunk by the memory cell in determining biasing states varies depending on the information stored therein. For example, to store information in a typical twin-transistor memory cell there is provided two different threshold voltage (Vt) values for the cell, with each different threshold voltage (Vt) value associated with a different logic or bit value.
Existing twin-cell multi-time programmable memory (MTPM) utilizes two transistors to store 1 bit of information, and uses a localized reference transistor for each cell. Use of twin-cells in MTPM open bitline architecture gives the highest density but suffers from sensing margin issues.
In a charge-trap memory, programming is achieved by altering the threshold voltage (Vt) of a field effect transistor (FET). In conventional twin-cell charge-trap memories, a pair of field effect transistors (FETs) are connected to true and complement bitlines and are controlled by a common wordline which controls the gates of the FETs. In a programming operation, programming voltages are applied to the cell and then a read verification is performed to check the adequacy of the programming. In this write-verify programming operation, a read signal margin test is performed to check a signal level to ensure the signal level is sufficient to overcome expected signal leakage and other signal detractors over the life of the memory.
In conventional charge-trap memory arrays, overcoming expected leakage and other signal detractors has been accomplished by imbalancing the sense amplifier to favor the opposite data state to make it more difficult to sense the expected data state. Further, when using the imbalanced sense amplifier approach, a current offset is applied to one side of the sense amplifier and an equivalent cell “signal” offset, or an equivalent change in a cell field effect transistor threshold voltage (FET Vt) is calculated. Further, in the conventional charge-trap memory arrays, an offset current of approximately 10 μa may be applied to one of the true or complement bitlines to correlate to an equivalent cell-programming offset of 10 mV of threshold voltage (Vt) shift. This signal margin approach is impacted by variation in cell current from process, voltage, and temperature (PVT). For example, a fast-process case will produce higher cell currents than a slow-process case and the current offset does not adjust accordingly. In fact, the current offset is fixed and may over test a slow-process chip and under test a fast-process chip. The accuracy of the signal margin approach may vary in a range from approximately 15 mV to 35 mV during a 20 mV signal margin test. This accuracy is acceptable for a one-time programmable memory (OTPM) array, but is not accurate enough to use in a multiple-time programmable memory (MTPM) array. In particular, the MTPM array may require operation with reduced signal levels.